Vertical transistors having a layer of charge carriers in the extension region for reduced extension region resistance

ABSTRACT

Embodiments of the invention are directed to a method of forming a semiconductor device. A non-limiting example of the method includes forming a fin having a fin bottom region. A charged region is formed on a sidewall of the fin bottom region, wherein the charged region includes charged particles, and wherein the fin bottom region is formed from an undoped semiconductor material. The charged particles attract charge carriers in the fin bottom region toward and adjacent to the sidewall of the fin bottom region, wherein the charge carriers form a current path through the undoped semiconductor material of the fin bottom region.

BACKGROUND

The present invention relates in general to semiconductor devices andtheir fabrication. More specifically, the present invention relates toimproved fabrication methodologies and resulting structures for verticalfield effect transistors (VFETs) configured and arranged to include alayer of charge carriers in the extension region of the channel fin,thereby reducing extension region resistance.

Semiconductor devices are typically formed using active regions of awafer. In an integrated circuit (IC) having a plurality of metal oxidesemiconductor field effect transistors (MOSFETs), each MOSFET has asource and a drain that are formed in an active region of asemiconductor layer by incorporating n-type or p-type impurities in thelayer of semiconductor material. A conventional geometry for MOSTFETs isknown as a planar device geometry in which the various parts of theMOSFET device are laid down as planes or layers.

A type of MOSFET is a non-planar FET known generally as a VFET. VFETsemploy semiconductor fins and side-gates that can be contacted outsidethe active region, resulting in increased device density and someincreased performance over lateral devices. In VFETs the source to draincurrent flows in a direction that is perpendicular to a major surface ofthe substrate. For example, in a known VFET configuration a majorsubstrate surface is horizontal and a vertical fin extends upward fromthe substrate surface. The fin forms the channel region of thetransistor. A source region and a drain region are situated inelectrical contact with the top and bottom ends of the channel region. Agate is disposed on one or more of the fin sidewalls.

SUMMARY

Embodiments of the invention are directed to a method of forming asemiconductor device. A non-limiting example of the method includesforming a fin having a fin bottom region. A charged region is formed ona sidewall of the fin bottom region, wherein the charged region includescharged particles, and wherein the fin bottom region is formed from anundoped semiconductor material. The charged particles attract chargecarriers in the fin bottom region toward and adjacent to the sidewall ofthe fin bottom region, wherein the charge carriers form a current paththrough the undoped semiconductor material of the fin bottom region.

Embodiments of the invention are directed to a method of forming asemiconductor device. A non-limiting example of the method includesforming a fin over a substrate, wherein the fin includes a fin bottomregion and a fin top region, wherein the fin bottom region comprises anundoped semiconductor material. A bottom source or drain (S/D) region isformed in or on the substrate. A charged region is formed on a sidewallof the fin bottom region, and the charged region includes chargedparticles. A bottom spacer is formed over the bottom S/D region andadjacent to the charged region. A gate stack is formed on a sidewall ofthe fin top region. A top spacer is formed on the sidewall of the fintop region and over the gate stack. A top S/D region is formed on a topsurface of the fin top region. The charged particles of the chargedregion attract charge carriers in the fin bottom region to the sidewallof the fin bottom region. The charge carriers form a fin bottom regioncurrent path configured to couple current from the bottom S/D regionthrough the undoped semiconductor material of the fin bottom region andinto the fin top region.

Embodiments of the invention are directed to a semiconductor device. Anon-limiting example of the semiconductor device includes a fin having afin bottom region, along with a charged region formed on a sidewall ofthe fin bottom region, wherein the charged region includes chargedparticles. The fin bottom region is formed from an undoped semiconductormaterial. The charged particles attract charge carriers in the finbottom region toward and adjacent to the sidewall of the fin bottomregion. The charge carriers form a current path through the undopedsemiconductor material of the fin bottom region.

Additional features and advantages are realized through the techniquesdescribed herein. Other embodiments and aspects are described in detailherein. For a better understanding, refer to the description and to thedrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter which is regarded as the present invention isparticularly pointed out and distinctly claimed in the claims at theconclusion of the specification. The foregoing and other features andadvantages are apparent from the following detailed description taken inconjunction with the accompanying drawings in which:

FIG. 1 depicts a cross-sectional view of a portion of a semiconductorstructure having a charge carrier current path formed at sidewalls of afin bottom region according to embodiments of the invention;

FIG. 2 depicts a cross-sectional view of a portion of anothersemiconductor structure having a charge carrier current path formed atsidewalls of a fin bottom region according to embodiments of theinvention;

FIG. 3 depicts a cross-sectional view of a portion of anothersemiconductor structure having a charge carrier current path formed atsidewalls of a fin bottom region according to embodiments of theinvention;

FIG. 4 depicts a cross-sectional view of a portion of anothersemiconductor device having a charge carrier current path formed atsidewalls of a fin bottom region according to embodiments of theinvention;

FIGS. 5-16 depict cross-sectional views of a semiconductor structureafter applying fabrication operations of a method for forming a finalVFET semiconductor device having a charge carrier current path formedthrough a bottom extension region according to embodiments of theinvention, in which:

FIG. 5 depicts a cross-sectional view of the semiconductor structureafter fabrication operations according to embodiments of the invention;

FIG. 6 depicts a cross-sectional view of the semiconductor structureafter fabrication operations according to embodiments of the invention;

FIG. 7 depicts a cross-sectional view of the semiconductor structureafter fabrication operations according to embodiments of the invention;

FIG. 8 depicts a cross-sectional view of the semiconductor structureafter fabrication operations according to embodiments of the invention;

FIG. 9 depicts a cross-sectional view of the semiconductor structureafter fabrication operations according to embodiments of the invention;

FIG. 10 depicts a cross-sectional view of the semiconductor structureafter fabrication operations according to embodiments of the invention;

FIG. 11 depicts a cross-sectional view of the semiconductor structureafter fabrication operations according to embodiments of the invention;

FIG. 12 depicts a cross-sectional view of the semiconductor structureafter fabrication operations according to embodiments of the invention;

FIG. 13 depicts a cross-sectional view of the semiconductor structureafter fabrication operations according to embodiments of the invention;

FIG. 14 depicts a cross-sectional view of the semiconductor structureafter fabrication operations according to embodiments of the invention;

FIG. 15 depicts a cross-sectional view of the semiconductor structureafter fabrication operations according to embodiments of the invention;and

FIG. 16 depicts a cross-sectional view of the semiconductor structureafter fabrication operations to form the final VFET semiconductor devicehaving a charge carrier current path formed at sidewalls of a fin bottomregion according to embodiments of the invention; and

FIG. 17 depicts a cross-sectional view of another semiconductorstructure after applying fabrication operations of a method for forminga final VFET semiconductor device having a charge carrier current pathformed through a bottom extension region according to embodiments of theinvention.

In the accompanying figures and following detailed description of theembodiments, the various elements illustrated in the figures areprovided with three or four digit reference numbers. The leftmostdigit(s) of each reference number corresponds to the figure in which itselement is first illustrated.

DETAILED DESCRIPTION

It is understood in advance that, although this description includes adetailed description of the formation and resulting structures for aspecific type of VFET, implementation of the teachings recited hereinare not limited to a particular type of VFET architecture or ICarchitecture. Rather embodiments of the present invention are capable ofbeing implemented in conjunction with any other type of fin-based FETarchitecture or IC architecture, now known or later developed.

For the sake of brevity, conventional techniques related tosemiconductor device and integrated circuit (IC) fabrication may or maynot be described in detail herein. Moreover, the various tasks andprocess steps described herein can be incorporated into a morecomprehensive procedure or process having additional steps orfunctionality not described in detail herein. In particular, varioussteps in the manufacture of semiconductor devices andsemiconductor-based ICs are well known and so, in the interest ofbrevity, many conventional steps will only be mentioned briefly hereinor will be omitted entirely without providing the well-known processdetails.

Turning now to an overview of technologies that are more specificallyrelevant to aspects of the present invention, as previously notedherein, some non-planar transistor device architectures, such as VFETs,employ semiconductor fins and side-gates that can be contacted outsidethe active region, resulting in increased device density over lateraldevices. In VFETs the source to drain current flows in a direction thatis perpendicular to a major surface of the substrate. For example, in aknown VFET configuration a major substrate surface is horizontal and avertical fin extends upward from the substrate surface. The fin formsthe channel region of the transistor. A source region and a drain regionare situated in electrical contact with the top and bottom ends of thechannel region, respectively, while a gate is disposed on and around oneor more of the fin sidewalls.

A bottom junction is formed at the interface between the channel fin andthe bottom source or drain (S/D) region, and a top junction is formed atthe interface between the channel fin and the top S/D region. Virtuallyall semiconductor transistors are based on the formation of junctions.Junctions are capable of both blocking current and allowing it to flow,depending on an applied bias. Junctions are typically formed by placingtwo semiconductor regions with opposite polarities into contact with oneanother. The most common junction is the p-n junction, which consists ofa contact between a p-type piece of silicon, rich in holes, and ann-type piece of silicon, rich in electrons. N-type and p-type FETs areformed by implanting different types of dopants to selected regions ofthe device to form the necessary junction(s). N-type devices can beformed by implanting, for example, arsenic (As) or phosphorous (P).P-type devices can be formed by implanting, for example, boron (B).After implanting the necessary dopants in the S/D regions, a dopantdrive-in anneal is applied to activate the dopants and drive (ordiffuse) dopants further into the channel fin, thereby extending thejunctions further into the channel fin. The regions that are doped bythe dopant drive-in anneal are known generally as extension regions, andthe junctions that are created by the dopant drive-in anneal are knowngenerally as extension junctions.

In a VFET architecture, the active channel of the fin is surrounded bythe gate, and the top/bottom S/D junctions must be positioned such thegate sufficiently overlaps the S/D junctions. If the gate does notsufficiently overlap the top/bottom S/D junctions (or extensionjunctions), external resistance (also known as extension resistance) isincreased and overall transistor performance is degraded. Due tolimitations in known semiconductor device processing capabilities, thebottom end of the fin can taper outward such that the fin's bottom endis wider than the fin's active channel region. Because the fin's bottomend is tapered, the anneal-based dopant drive-in cannot drive/diffuseenough dopants from the bottom S/D region to fill in the extra areacreated by the tapered bottom end. As a result, a portion of the bottomextension region remains undoped, the gate does not sufficiently overlapthe bottom extension junction, and the resistance in the bottomextension region is increased, all of which degrade transistorperformance.

Turning now to an overview of aspects of the invention, embodiments ofthe invention provide fabrication methodologies and resultingstructures, wherein improved control over resistance in the bottomextension region is provided by forming a layer or sheet of chargecarriers in the bottom extension region. In embodiments of theinvention, the charge carrier layer/sheet is formed by attractingcharged particles such that they are concentrated within an area thatdefines the layer/sheet. Within the layer/sheet, the charged particlesare majority charge carriers capable of providing a conductive paththrough the layer/sheet for carrying current. In embodiments of theinvention, the majority charge carriers can be free electrons (i.e.,negative charge carriers) for n-type FET structures or free holes (i.e.,positive charge carriers) for p-type FET structures. The charge carrierlayer/sheet provides the conductive path through the bottom extensionregion even though portions of the bottom extension region remainundoped and the gate does not sufficiently laterally overlap the bottomextension junction.

In some embodiments of the invention, the charge carrier layer/sheet isformed adjacent to a sidewall of the bottom extension region. In someembodiments of the invention, the charge carrier layer/sheet is createdby depositing a charged region/layer on the sidewall of the bottomextension region. The charged region/layer is configured to includecharged particles that attract opposite polarity charged particles inthe bottom extension region toward the bottom extension region sidewall,thereby creating the previously-described charge carrier layer/sheet.For n-type FET architectures where the majority carriers are electrons,the charge carriers in the charge carrier layer/sheet are electrons, andthe charged particles in charged layer/region are positive charges. Forp-type FET architecture where the majority carriers are holes, thecharge carriers in the charge carrier layer/sheet are holes, and thecharged particles in charged layer/region are negative charges. 0

In some embodiments of the invention, the charged particles in thecharged layer/region are dipoles, and the charged layer/region includesa bi-layer structure formed from an interfacial layer and a metal oxidelayer. The interfacial layer includes positive charges, and the metaloxide layer includes negative charges. The dipoles are pairs of chargedparticles formed from one of the positive charges in the positive chargelayer separated from one of the negative charges in the negative chargelayer by a predetermined distance. For NFET architectures where themajority carriers are electrons, the interfacial layer is formed on thesidewall of the bottom extension region, and the metal oxide layer isdeposited on the interfacial layer. Thus, the positive charges of thedipoles attract negatively charged particles (e.g., electrons) in thebottom extension region toward and adjacent to the sidewall of thebottom extension region, thereby forming the previously-described chargecarrier layer/sheet that provides the conductive path for current toflow through the undoped portion of the bottom extension region. Inembodiments of the invention, the interfacial layer and the metal oxidelayer are formed from materials that are known to generate dipoles whenlayered one on top of another. In NFET architectures, the interfaciallayer can be formed from a variety of suitable dipole-forming materials,including, for example, SiO₂, GeO₂, and mixture thereof, and the metaloxide layer can be formed from a variety of suitable dipole-formingmaterials, including, for example, Y₂O₃, Lu₂O₃, La₂O₃, and SrO. For PFETarchitectures where the majority carriers are holes, the interfaciallayer is formed on the sidewall of the bottom extension region, and themetal oxide layer is formed on the negative charge layer. Thus, thenegative charges of the dipoles attract positively charged particles(.e.g., holes) in the bottom extension region toward and adjacent to thesidewalls of the bottom extension, thereby forming thepreviously-described charge carrier layer/sheet that provides theconductive path for current to flow through the undoped portions of thebottom extension region. In PFET architectures, the interfacial layercan be formed from a variety of suitable dipole-forming materials,including, for example, SiO₂, GeO₂, and mixture thereof, and the metaloxide layer can be formed from a variety of suitable dipole-formingmaterials, including, for example, Al₂O₃, TiO₂.

In some embodiments of the invention, the charged particles in thecharged region/layer are created by dopants in the charged region/layer.Based on the type of dopant used, the dopants either give off negativelycharged particles (e.g., electrons) to the conduction band of the dopedcharged region/layer, or the dopants give off holes to the valence bandof the doped charged region/layer. For NFET architectures where themajority carriers are electrons, the charged particles in the chargedregion/layer are positively charged, and the charged region/layer can beformed from a variety of suitable materials and dopants, including, forexample, SiO₂ doped with nitrogen (N) or GeO₂ doped with N. Any suitabledoping process can be used to dope the charged region/layer, including,for example, ion implantation or annealing the charged region/layer inan ambient that includes the dopant (e.g., N). For PFET architectureswhere the majority carriers are holes, the charged particles in thecharged layer/region are negatively charged, and the chargedlayer/region can be formed from a variety of suitable materials anddopants, including, for example, SiO₂ doped with fluorine (F) or GeO₂doped with F. Any suitable doping process can be used to dope thecharged region/layer, including, for example, ion implantation orannealing the charged region/layer in an ambient that includes thedopant (e.g., F).

Turning now to a more detailed description of embodiments of theinvention, FIG. 1 depicts a cross-sectional view of selected portions ofa semiconductor structure 500A having a charge carrier current pathdefined by a layer/sheet of charged particles 902 extending through afin bottom region 214 according to embodiments of the invention. Whenthe fabrication operations are completed, the semiconductor structure500A will form an n-type VFET device, an example of which is the finaln-type VFET device 500C shown in FIG. 16. The selected portions of thesemiconductor structure 500A shown in FIG. 1 include a fin formed from afin top region 212 and a fin bottom region 214. The fin bottom region214 will be the bottom extension region of the final VFET 500. Bottomspacers 802 are formed around the fin bottom region 214. To betterillustrate aspects of the invention, a region 110 of the structure 500Ahaving a layer/sheet of charged particles 902 and a charged region/layer701 has been enlarged.

Due to limitations in known semiconductor device processingcapabilities, the fin bottom region 214 tapers outward such that the finbottom region 214 is wider than the fin top region 212. Because the finbottom region 214 is tapered, the anneal-based dopant drive-in that isapplied to the bottom S/D region (e.g., bottom S/D region 602 shown inFIG. 6) cannot drive/diffuse enough dopants from the bottom S/D regioninto the fin bottom region 214 to fill in the extra area created by thetaper. As a result, even after the dopant drive-in, a portion of the finbottom region 214 (i.e., the bottom extension region) remains undoped.If not addressed, the undoped fin bottom region 214 increases resistancein the bottom extension region and degrades transistor performance.Aspects of the invention overcome increased resistance in the fin bottomregion 214 by providing a conductive path through the undoped materialof the fin bottom region 214 (i.e., the bottom extension region). Asshown in FIG. 1, the conductive path is provided by the layer/sheet ofcharged particles 902 formed adjacent to a sidewall of the fin bottomregion 214. In accordance with aspects of the invention, the layer/sheetof charged particles 902 have been attracted toward sidewalls of the finbottom region 214 such that the charged particles 902 are concentratedwithin an area that defines the layer/sheet. Within the layer/sheet ofcharged particles 902, the charged particles 902 function as majoritycharge carriers capable of providing a conductive path through thelayer/sheet for carrying current through the fin bottom region 214.

In aspects of the invention, the layer/sheet of charged particles 902 iscreated by depositing a charged region/layer 701 on the sidewall of thefin bottom region 214 prior to forming the bottom spacers 802. Thecharged region/layer 701 is configured to include a bi-layer structureformed from an interfacial layer 702 and a metal oxide layer 704. Theinterfacial layer 702 includes positive charges, and the metal oxidelayer 704 includes negative charges. The charged region/layer 701 formsdipoles from the positive charges in the interfacial layer 702 andnegative charges in the metal oxide layer 704. More specifically, thedipoles are pairs of charged particles formed from one of the positivecharges in the interfacial layer 702 separated from one of the negativecharges in the metal oxide layer 704 by a predetermined distance.Because the semiconductor structure 500A will be an n-type FETarchitecture where the majority carriers are electrons, the interfaciallayer 702 is formed on the sidewall of the fin bottom region 214, andthe metal oxide layer 704 is deposited on the interfacial layer 702.Thus, the positive charges of the dipoles formed in the chargeregion/layer 701 attract negative charged particles 902 (e.g.,electrons) in the fin bottom region 214 toward and adjacent to thesidewall of the fin bottom region 214, thereby forming the layer/sheetof charged particles 902 that provides a conductive path for current toflow through the fin bottom region 214. The interfacial layer 702 can beformed from a variety of suitable dipole-forming materials, including,for example, SiO₂, GeO₂, and mixture thereof, and the metal oxide layer704 can be formed from a variety of suitable dipole-forming materials,including, for example, Y₂O₃, Lu₂O₃, La₂O₃, and SrO.

FIG. 2 depicts a cross-sectional view of selected portions of asemiconductor structure 500B having a charge carrier current pathdefined by a layer/sheet of charged particles 902A extending through thefin bottom region 214 according to embodiments of the invention. Whenfabrication operations are completed, the semiconductor structure 500Bwill form a p-type VFET device. As shown in FIG. 2, the selectedportions of the semiconductor structure 500B include a fin formed from afin top region 212 and a fin bottom region 214. The fin bottom region214 will be the bottom extension region of the final p-type VFET device.Similar to the structure 500A (shown in FIG. 1), the fin bottom region214 of the structure 500B is tapered such that the fin bottom region 214is wider than the fin top region 212. Bottom spacers 802 are formedaround the fin bottom region 214. To better illustrate aspects of theinvention, a region 110A of the structure 500B having a layer/sheet ofcharged particles 902A and a charged region/layer 701A has beenenlarged.

As shown in FIG. 2, the layer/sheet of charged particles 902A is formedadjacent to a sidewall of the fin bottom region 214 (i.e., the bottomextension region). In accordance with aspects of the invention, thelayer/sheet of charged particles 902A has been attracted towardsidewalls of the fin bottom region 214 such that the charged particles902A are concentrated within an area that defines the layer/sheet.Within the layer/sheet of charged particles 902A, the charged particles902 function as majority charge carriers capable of providing aconductive path through the layer/sheet for carrying current through thefin bottom region 214.

In aspects of the invention, the layer/sheet of charged particles 902Ais created by depositing a charged region/layer 701A on the sidewall ofthe fin bottom region 214 prior to forming the bottom spacers 802. Thecharged region/layer 701A is configured to include a bi-layer structureformed from an interfacial layer 704A and a metal oxide layer 702A. Theinterfacial layer 704A includes negative charges, and the metal oxidelayer 702A includes positive charges. The charged region/layer 701Aforms dipoles from the negative charges in the interfacial layer 704Aand positive charges in the metal oxide layer 702A. More specifically,the dipoles are pairs of charged particles formed from one of thenegative charges in the interfacial layer 704A separated from one of thepositive charges in the metal oxide layer 702A by a predetermineddistance. Because the semiconductor structure 500B will afterfabrication is completed be a p-type FET architecture where the majoritycarriers are holes, the interfacial layer 704A is formed on the sidewallof the fin bottom region 214, and the metal oxide layer 702A isdeposited on the interfacial layer 704A. Thus, the negative charges ofthe dipoles formed in the charge region/layer 701A attract positivecharged particles 902A (e.g., holes) in the fin bottom region 214 towardand adjacent to the sidewall of the fin bottom region 214, therebyforming the layer/sheet of charged particles 902A that provides aconductive path for current to flow through the fin bottom region 214.The interfacial layer 704A can be formed from a variety of suitabledipole-forming materials, including, for example, SiO₂, GeO₂, andmixture thereof, and the metal oxide layer 702A can be formed from avariety of suitable dipole-forming materials, including, for example,Al₂O₃, TiO₂.

FIG. 3 depicts a cross-sectional view of selected portions of asemiconductor structure 600A having a charge carrier current pathdefined by a layer/sheet of charged particles 1902 extending through thefin bottom region 214 according to embodiments of the invention. Whenfabrication operations are completed, the semiconductor structure 600Awill form an n-type VFET device, an example of which is the final n-typeVFET device 500 shown in FIG. 16. As shown in FIG. 3, the selectedportions of the semiconductor structure 600A include a fin formed from afin top region 212 and a fin bottom region 214. The fin bottom region214 will be the bottom extension region of the final p-type VFET device.Similar to the structure 500A (shown in FIG. 1), the fin bottom region214 of the structure 600A is tapered such that the fin bottom region 214is wider than the fin top region 212. Bottom spacers 802 are formedaround the fin bottom region 214, and bottom S/D regions 602 are formedin a substrate 502.

In aspects of the invention, the layer/sheet of charged particles 1902is created by depositing a charged region/layer 1702 on the sidewall ofthe fin bottom region 214 prior to forming the bottom spacers 802. Inembodiments of the invention, the charged layer/region 1702 includescharged particles (not shown) created by dopants in the chargedregion/layer 1702. Based on the type of dopant used, the dopants eithergive off negatively charged particles (e.g., electrons) to theconduction band of the doped charged region/layer 1702, or the dopantsgive off holes to the valence band of the doped charged region/layer1702. For the n-type FET architecture shown in FIG. 3, the majoritycarriers are electrons, the charged particles in the chargedregion/layer 1702 are positively charged, and the charged region/layer1702 can be formed from a variety of suitable materials and dopants,including, for example, SiO₂ doped with nitrogen (N) or GeO₂ doped withN. Any suitable doping process can be used to dope the chargedregion/layer 1702, including, for example, ion implantation.

FIG. 4 depicts a cross-sectional view of selected portions of asemiconductor structure 600B having a charge carrier current pathdefined by a layer/sheet of charged particles 1902A extending throughthe fin bottom region 214 according to embodiments of the invention.When fabrication operations are completed, the semiconductor structure600B will form a p-type VFET device. As shown in FIG. 4, the selectedportions of the semiconductor structure 600B include a fin formed from afin top region 212 and a fin bottom region 214. The fin bottom region214 will be the bottom extension region of the final n-type VFET device.Similar to the structure 500A (shown in FIG. 1), the fin bottom region214 of the structure 600B is tapered such that the fin bottom region 214is wider than the fin top region 212. Bottom spacers 802 are formedaround the fin bottom region 214, and bottom S/D regions 602 are formedin a substrate 502.

In aspects of the invention, the layer/sheet of charged particles 1902Ais created by depositing a charged region/layer 1702A on the sidewall ofthe fin bottom region 214 prior to forming the bottom spacers 802. Inembodiments of the invention, the charged layer/region 1702A includescharged particles (not shown) created by dopants in the chargedregion/layer 1702A. Based on the type of dopant used, the dopants eithergive off negatively charged particles (e.g., electrons) to theconduction band of the doped charged region/layer 1702A, or the dopantsgive off holes to the valence band of the doped charged region/layer1702A. For the p-type FET architecture shown in FIG. 4, the majoritycarriers are holes, the charged particles in the charged region/layer1702A are negatively charged, and the charged layer/region 1702A can beformed from a variety of suitable materials and dopants, including, forexample, SiO₂ doped with fluorine (F) or GeO₂ doped with F. Any suitabledoping process can be used to dope the charged region/layer 1702A,including, for example, annealing the charged region/layer 1702A in anambient that includes the dopant (e.g., F).

FIGS. 5-16 depict two-dimensional (2D) cross-sectional views of asemiconductor structure 500 after fabrication operations of a method forforming a final n-type VFET semiconductor device 500C (shown in FIG. 16)having a charge carrier current path (e.g., layer/sheet of chargedparticles 902 shown in FIG. 9) formed at sidewalls of the fin bottomregion 214 according to embodiments of the invention. The fabricationoperations depicted in FIGS. 5-16 apply equally to the fabrication of ap-type VFET in accordance with aspects of the invention with theappropriate polarity changes for the p-type structure. As shown in FIG.5, known semiconductor fabrication operations have been used to form thesemiconductor structure 500 having a substrate 502 and a fin 502 thatincludes a fin top region 212, a fin bottom region 214, and a hardmask220. With reference to the X/Y/Z diagrams depicted in the figures, thevarious elements that form the semiconductor structure 500 extend alonga first axis (e.g., X-axis) to define width dimensions, and extend alonga second axis (e.g., Y-axis) perpendicular to the X-axis to defineheight (or thickness) dimensions. Although not specifically depicted inthe 2D cross-sectional views shown in FIGS. 5-16, the various elementsthat form the semiconductor structure 500 and/or the final n-type VFETdevice 500C (shown in FIG. 16) also extend along a third axis (e.g.,Z-axis) perpendicular to the first axis and the second axis to definedepth dimensions. In accordance with standard VFET architectures,various elements of the semiconductor structures 500 and the n-type VFET500C (e.g., bottom spacer 802, interfacial layer 1002, high-k dielectric1004, WFM 1006, etc.) extend completely around the sidewalls of the fin502 in the X, Y, and Z directions.

The substrate 502 can be any suitable substrate material, such as, forexample, monocrystalline Si, SiGe, SiC, III-V compound semiconductor,II-VI compound semiconductor, or semiconductor-on-insulator (SOI). Insome embodiments of the invention, the substrate 502 includes a buriedoxide layer (not depicted).

The fin 502 can be formed by depositing a hard mask layer (not shown)over the substrate 502 using any suitable deposition process. The hardmask layer can be a dielectric such as silicon nitride (SiN), siliconoxide, or a combination of silicon oxide and silicon nitride.Conventional semiconductor device fabrication processes (e.g.,patterning and lithography, self-aligned double patterning, self-alignedquadruple patterning) are used to remove portions of the substrate 502and the hard mask layer to form the fin 502 and the hard mask 220. Forexample, the hard mask layer can be patterned to expose portions of thesubstrate 502. The exposed portions of the substrate 502 can then beremoved or recessed using, for example, a wet etch, a dry etch, or acombination thereof, to thereby form the fin 502 and the hard mask 220.Due to limitations in known semiconductor device processingcapabilities, the fin bottom region 214 tapers outward such that the finbottom region 214 is wider than the fin top region 212. The fin 502 canbe electrically isolated from other regions of the substrate 502 by ashallow trench isolation region (not depicted). The shallow trenchisolation region can be of any suitable dielectric material, such as,for example, a silicon oxide.

In FIG. 6, known fabrication operations have been used to form a bottomS/D region 602 in the substrate 502. In some embodiments of theinvention, the bottom S/D region 602 can be formed later in thefabrication process. In some embodiments of the invention, the bottomS/D region 602 is epitaxially grown, and the necessary doping to formthe bottom S/D region 204 is provided through in-situ doping during theepitaxial growth process, or through ion implantation after the bottomS/D region 204 is formed. The bottom S/D region 602 can be formed by anysuitable doping technique, including but not limited to, ionimplantation, gas phase doping, plasma doping, plasma immersion ionimplantation, cluster doping, infusion doping, liquid phase doping,solid phase doping, in-situ epitaxy growth, or any suitable combinationof those techniques.

After providing the necessary dopants in the bottom S/D regions 602, adopant drive-in anneal is applied to activate the dopants and drive (ordiffuse) dopants further into the fin bottom region 214, therebyextending the junctions formed at the SD region/fin interface furtherinto the fin bottom region 214. The regions of the fin bottom channel214 that are doped by the dopant drive-in anneal are known generally asextension regions, and the junctions that are created by the dopantdrive-in anneal are known generally as extension junctions. Because thefin bottom region 214 is tapered, the anneal-based dopant drive-in thatis applied to the bottom S/D regions 602 cannot drive/diffuse enoughdopants from the bottom S/D regions 602 into the fin bottom region 214to fill in the extra area created by the taper. As a result, even afterthe dopant drive-in, a portion of the fin bottom region 214 (i.e., thebottom extension region) remains undoped.

In FIG. 7, known fabrication operations have been used to conformallydeposit a charged layer/region 701 over the semiconductor structure 500.In embodiments of the invention, the charged layer/region 701 is abi-layer structure having an interfacial layer 702 and a metal oxidelayer 704. The interfacial layer 702 includes positive charges, and themeatl oxide layer 704 includes negative charges for n-type FET. Thecharged region/layer 701 forms dipoles from the positive charges in theinterfacial layer 702 and negative charges in the metal oxide layer 704.More specifically, the dipoles are pairs of charged particles formedfrom one of the positive charges in the interfacial layer 702 separatedfrom one of the negative charges in the metal oxide layer 04 by apredetermined distance. Because the semiconductor structure 500 will bean n-type FET architecture where the majority carriers are electrons,the interfacial layer 702 is deposited over the structure 500, and themetal oxide layer 704 is deposited on the interfacial layer 702. Thus,the positive charges of the dipoles formed in the charge region/layer701 attract negative charged particles 902 (shown in FIG. 9) in the finbottom region 214 toward and adjacent to the sidewall of the fin bottomregion 214, thereby forming the layer/sheet of charged particles 902that provides a conductive path for current to flow through the finbottom region 214. The interfacial layer 702 can be formed from avariety of suitable dipole-forming materials, including, for example,SiO₂, GeO₂, and mixture thereof, and the metal oxide layer₂O₃, Lu₂O₃,La₂O₃, and SrO.

In FIG. 8, known fabrication operations have been used to form thebottom spacers 802 over the charged region/layer 701 and across from thefin bottom region 214. The bottom spacers 802 can include a dielectricmaterial, such as, for example, SiN, SiC, SiOC, SiCN, BN, SiBN, SiBCN,SiOCN, SiO_(x)N_(y), and combinations thereof. The dielectric materialcan be a low-k material having a dielectric constant less than about 7,less than about 5, or even less than about 2.5. The bottom spacers 802can be formed using known deposition processes, such as, for example,CVD, PECVD, ALD, PVD, chemical solution deposition, or other likeprocesses.

In FIG. 9, known fabrication operations have been used to selectivelyremove the metal oxide layer 704 and the interfacial layer 702 from thefin top region 212 and the hard mask 220.

In FIG. 10, an interfacial layer 1002, a high-k dielectric 1004, and awork function metal (WFM) 1006 have been deposited over the bottomspacers 802, the fin top region 212, and the hard mask 220. The high-kdielectric layer 1004 can be formed from one or more films, examples ofwhich include oxides, nitrides, oxynitrides, silicates (e.g., metalsilicates), aluminates, titanates, nitrides, or any combination thereof.Examples of high-k materials with a dielectric constant greater than 7.0include, but are not limited to, metal oxides such as hafnium oxide,hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide,lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide,zirconium silicon oxynitride, tantalum oxide, titanium oxide, bariumstrontium titanium oxide, barium titanium oxide, strontium titaniumoxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, andlead zinc niobate. The high-k dielectric layer 1004 can further includedopants such as, for example, lanthanum and aluminum. The dielectriclayers 1002, 1004 can be formed by suitable deposition processes, forexample, CVD, PECVD, atomic layer deposition (ALD), evaporation,physical vapor deposition (PVD), chemical solution deposition, or otherlike processes. The thickness of the dielectric layers 1002, 1004 canvary depending on the deposition process as well as the composition andnumber of high-k dielectric materials used.

The WFM 1006 can be deposited over the dielectric layers 1002, 1004 by asuitable deposition process, for example, ALD, CVD, PECVD, PVD, plating,thermal or e-beam evaporation, and sputtering. The type of WFM dependson the type of transistor and can differ between the nFET and pFETdevices. P-type WFMs include compositions such as titanium nitride,tungsten, ruthenium, palladium, platinum, cobalt, nickel, and conductivemetal oxides, or any combination thereof. N-type WFMs includecompositions such as hafnium, zirconium, titanium, tantalum, aluminum,metal carbides (e.g., hafnium carbide, zirconium carbide, titaniumcarbide, and aluminum carbide), aluminides, or any combination thereof.

In FIG. 11, known fabrication operations have been used to deposit anorganic planarization layer (OPL) 1102 over the structure 500. Ingeneral, OPLs are used as etch masks for pattern transfers intoinorganic substrates, to fill pre-existing features, and to planarizethe substrate to allow for larger patterning process windows. After theOPL 1102 has been deposited, known fabrication operations have been usedto recess the interlayer dielectric 1002, the high-k dielectric 1004,the WFM 1106, and the OPL 1102 to a level below a top surface of the fintop region 212 using, for example, etching process.

In FIG. 12, known fabrication operations have been used to conformallydeposit an encapsulating layer 1202 over the structure 500. Theencapsulating layer 1202 includes a portion positioned over the WFM 1006and adjacent to the fin top region 212 will function as the top spacerof the final n-type VFET 500C (shown in FIG. 16). The encapsulatinglayer 1202 can include a dielectric material, such as, for example, SiN,SiC, SiOC, SiCN, BN, SiBN, SiBCN, SiOCN, SiO_(x)N_(y), and combinationsthereof. The dielectric material can be a low-k material having adielectric constant less than about 7, less than about 5, or even lessthan about 2.5. The encapsulating layer 1202 can be formed using knowndeposition processes, such as, for example, CVD, PECVD, ALD, PVD,chemical solution deposition, other directional deposition techniques,or other like processes.

In FIG. 13, known fabrication operations have been used to deposit aninterlayer dielectric (ILD) material 1302 over the over the structure500. In embodiments of the invention, the ILD material 1302 can be anysuitable material, including, for example, SiO₂. After the ILD material1302 has been deposited, known fabrication operations have been used toplanarize the structure 500 using, for example, CMP.

In FIG. 14, known fabrication operations have been used to recess thefill-in material 1302 and the encapsulation layer 1202 to a level belowa top surface of the fin top region 212 using, for example, etchingprocess. The recess operations also remove the hard mask 220.

In FIG. 15, known fabrication operations have been used to form a topS/D region 1502 on the top surface and exposed sidewalls of the fin topregion 212. In embodiments of the invention, the top S/D region 1502 isepitaxially grown, and the necessary doping to form the top S/D region1502 is provided through in-situ doping during the epitaxial growthprocess, or through ion implantation after the top S/D region 1502 isformed. The top S/D region 1502 can be formed by any suitable dopingtechnique, including but not limited to, ion implantation, gas phasedoping, plasma doping, plasma immersion ion implantation, clusterdoping, infusion doping, liquid phase doping, solid phase doping,in-situ epitaxy growth, or any suitable combination of those techniques.

In FIG. 16, known fabrication operations have been used to deposit anadditional layer of the encapsulation material 1202, along withadditional ILD material 1302A over the additional layer of encapsulationmaterial 1202. A S/D contact 1602 is formed in the ILD material 1302A tocontact the top S/D region 1502. In embodiments of the invention, theS/D contact 1602 can be formed by forming a trench in the ILD material1302A. The trench is positioned over the top S/D region 1502 to whichelectrical coupling will be made. A liner/barrier material is depositedwithin the trench, and the remaining trench volume is filled with copperusing, for example, a chemical/electroplating process, to thereby formthe S/D contact 1602. The excess copper is removed to form a flatsurface for subsequent processing. A cap layer (not shown) can bedeposited over the exposed top surface of the S/D contact 1602.

FIG. 17 depicts a 2D cross-sectional views of a semiconductor structure600 after fabrication operations of a method for forming a final n-typeVFET device having a charge carrier current path embodied in alayer/sheet of charged particles 1902 formed at sidewalls of the finbottom region 214 according to embodiments of the invention. Thefabrication operations depicted in FIG. 17 apply equally to thefabrication of a p-type VFET in accordance with aspects of the inventionwith the appropriate polarity changes for the p-type structure. As shownin FIG. 15, the fabrication operations shown in FIGS. 1 and 2 have beenused to form the semiconductor device 600 having a substrate 502, a fintop region 212, a fin bottom region 214, a hard mask 220, and bottom S/Dregions 602, configured and arranged as shown. The structure 600 differsfrom the structure 500 (shown in FIGS. 1-15) in that, at the fabricationstage shown in FIG. 17, a charged layer/region 1702 is deposited overthe structure 600.

In some embodiments of the invention, the layer/sheet of chargedparticles 1902 is created by depositing the charged region/layer 1702 onthe sidewall of the fin bottom region 214. The charged region/layer 1702is configured to include charged particles that attract oppositepolarity charged particles in the fin bottom region 214 toward thesidewall of the fin bottom region 214, thereby creating the layer/sheetof charged particles 1902. For n-type FET architectures where themajority carriers are electrons, the charge carriers in the chargecarrier layer/sheet are electrons, and the charged particles in chargedlayer/region are positively charged. For p-type FET architectures wherethe majority carriers are holes, the charge carriers 1902 in the chargecarrier layer/sheet are holes, and the charged particles in chargedlayer/region 1702 are negatively charged.

In embodiments of the invention, the charged layer/region 1702 includescharged particles (not shown) created by dopants in the chargedregion/layer 1702. Based on the type of dopant used, the dopants eithergive off negatively charged particles (e.g., electrons) to theconduction band of the doped charged region/layer 1702, or the dopantsgive off holes to the valence band of the doped charged region/layer1702. For the n-type FET architecture shown in FIG. 17, the majoritycarriers are electrons, the charged particles in the chargedregion/layer 1702 are positively charged, and the charged region/layer1702 can be formed from a variety of suitable materials and dopants,including, for example, SiO₂ doped with nitrogen (N) or GeO₂ doped withN. Any suitable doping process can be used to dope the chargedregion/layer 1702, including, for example, ion implantation or anitridation process that includes annealing the charged region/layer1702 in an ambient that includes the dopant (e.g., N).

In embodiments of the invention where the final VFET is a p-type FET,the majority carriers are holes, the charged particles (e.g., electrons)in the charged region/layer 1702 are negatively charged, and the chargedlayer/region 1702 can be formed from a variety of suitable materials anddopants, including, for example, SiO₂ doped with fluorine (F) or GeO₂doped with F. Any suitable doping process can be used to dope thecharged region/layer 1702, including, for example, ion implantation or afluorination process that includes annealing the charged region/layer1702 in an ambient that includes the dopant (e.g., F).

The remaining fabrication operations used to complete the structure 600are the same fabrication operations shown in FIGS. 8-16, wherein thecharged region/layer 701 is replaced with the charged region/layer 1702(shown in FIG. 17).

The methods described herein are used in the fabrication of IC chips.The resulting integrated circuit chips can be distributed by thefabricator in raw wafer form (that is, as a single wafer that hasmultiple unpackaged chips), as a bare die, or in a packaged form. In thelatter case the chip is mounted in a single chip package (such as aplastic carrier, with leads that are affixed to a motherboard or otherhigher level carrier) or in a multichip package (such as a ceramiccarrier that has either or both surface interconnections or buriedinterconnections). In any case the chip is then integrated with otherchips, discrete circuit elements, and/or other signal processing devicesas part of either (a) an intermediate product, such as a motherboard, or(b) an end product. The end product can be any product that includesintegrated circuit chips, ranging from toys and other low-endapplications to advanced computer products having a display, a keyboardor other input device, and a central processor.

Various embodiments of the present invention are described herein withreference to the related drawings. Alternative embodiments can bedevised without departing from the scope of this invention. Althoughvarious connections and positional relationships (e.g., over, below,adjacent, etc.) are set forth between elements in the followingdescription and in the drawings, persons skilled in the art willrecognize that many of the positional relationships described herein areorientation-independent when the described functionality is maintainedeven though the orientation is changed. These connections and/orpositional relationships, unless specified otherwise, can be direct orindirect, and the present invention is not intended to be limiting inthis respect. Similarly, the term “coupled” and variations thereofdescribes having a communications path between two elements and does notimply a direct connection between the elements with no interveningelements/connections between them. All of these variations areconsidered a part of the specification. Accordingly, a coupling ofentities can refer to either a direct or an indirect coupling, and apositional relationship between entities can be a direct or indirectpositional relationship. As an example of an indirect positionalrelationship, references in the present description to forming layer “A”over layer “B” include situations in which one or more intermediatelayers (e.g., layer “C”) is between layer “A” and layer “B” as long asthe relevant characteristics and functionalities of layer “A” and layer“B” are not substantially changed by the intermediate layer(s).

The following definitions and abbreviations are to be used for theinterpretation of the claims and the specification. As used herein, theterms “comprises,” “comprising,” “includes,” “including,” “has,”“having,” “contains” or “containing,” or any other variation thereof,are intended to cover a non-exclusive inclusion. For example, acomposition, a mixture, process, method, article, or apparatus thatcomprises a list of elements is not necessarily limited to only thoseelements but can include other elements not expressly listed or inherentto such composition, mixture, process, method, article, or apparatus.

Additionally, the term “exemplary” is used herein to mean “serving as anexample, instance or illustration.” Any embodiment or design describedherein as “exemplary” is not necessarily to be construed as preferred oradvantageous over other embodiments or designs. The terms “at least one”and “one or more” are understood to include any integer number greaterthan or equal to one, i.e. one, two, three, four, etc. The terms “aplurality” are understood to include any integer number greater than orequal to two, i.e. two, three, four, five, etc. The term “connection”can include an indirect “connection” and a direct “connection.”

References in the specification to “one embodiment,” “an embodiment,”“an example embodiment,” etc., indicate that the embodiment describedcan include a particular feature, structure, or characteristic, butevery embodiment may or may not include the particular feature,structure, or characteristic. Moreover, such phrases are not necessarilyreferring to the same embodiment. Further, when a particular feature,structure, or characteristic is described in connection with anembodiment, it is submitted that it is within the knowledge of oneskilled in the art to affect such feature, structure, or characteristicin connection with other embodiments whether or not explicitlydescribed.

For purposes of the description hereinafter, the terms “upper,” “lower,”“right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” andderivatives thereof shall relate to the described structures andmethods, as oriented in the drawing figures. The terms “overlying,”“atop,” “on top,” “positioned on” or “positioned atop” mean that a firstelement, such as a first structure, is present on a second element, suchas a second structure, wherein intervening elements such as an interfacestructure can be present between the first element and the secondelement. The term “direct contact” means that a first element, such as afirst structure, and a second element, such as a second structure, areconnected without any intermediary conducting, insulating orsemiconductor layers at the interface of the two elements.

Spatially relative terms, e.g., “beneath,” “below,” “lower,” “above,”“upper,” and the like, can be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the term “below” can encompass both an orientation ofabove and below. The device can be otherwise oriented (rotated 90degrees or at other orientations) and the spatially relative descriptorsused herein interpreted accordingly.

The terms “about,” “substantially,” “approximately,” and variationsthereof, are intended to include the degree of error associated withmeasurement of the particular quantity based upon the equipmentavailable at the time of filing the application. For example, “about”can include a range of ±8% or 5%, or 2% of a given value.

The phrase “selective to,” such as, for example, “a first elementselective to a second element,” means that the first element can beetched and the second element can act as an etch stop.

The term “conformal” (e.g., a conformal layer) means that the thicknessof the layer is substantially the same on all surfaces, or that thethickness variation is less than 15% of the nominal thickness of thelayer.

The terms “epitaxial growth and/or deposition” and “epitaxially formedand/or grown” mean the growth of a semiconductor material (crystallinematerial) on a deposition surface of another semiconductor material(crystalline material), in which the semiconductor material being grown(crystalline overlayer) has substantially the same crystallinecharacteristics as the semiconductor material of the deposition surface(seed material). In an epitaxial deposition process, the chemicalreactants provided by the source gases can be controlled and the systemparameters can be set so that the depositing atoms arrive at thedeposition surface of the semiconductor substrate with sufficient energyto move about on the surface such that the depositing atoms orientthemselves to the crystal arrangement of the atoms of the depositionsurface. An epitaxially grown semiconductor material can havesubstantially the same crystalline characteristics as the depositionsurface on which the epitaxially grown material is formed. For example,an epitaxially grown semiconductor material deposited on a {100}orientated crystalline surface can take on a {100} orientation. In someembodiments of the invention, epitaxial growth and/or depositionprocesses can be selective to forming on semiconductor surface, andcannot deposit material on exposed surfaces, such as silicon dioxide orsilicon nitride surfaces.

As previously noted herein, for the sake of brevity, conventionaltechniques related to semiconductor device and integrated circuit (IC)fabrication may or may not be described in detail herein. By way ofbackground, however, a more general description of the semiconductordevice fabrication processes that can be utilized in implementing one ormore embodiments of the present invention will now be provided. Althoughspecific fabrication operations used in implementing one or moreembodiments of the present invention can be individually known, thedescribed combination of operations and/or resulting structures of thepresent invention are unique. Thus, the unique combination of theoperations described in connection with the fabrication of asemiconductor device according to the present invention utilize avariety of individually known physical and chemical processes performedon a semiconductor (e.g., silicon) substrate, some of which aredescribed in the immediately following paragraphs.

In general, the various processes used to form a micro-chip that will bepackaged into an IC fall into four general categories, namely, filmdeposition, removal/etching, semiconductor doping andpatterning/lithography. Deposition is any process that grows, coats, orotherwise transfers a material onto the wafer. Available technologiesinclude physical vapor deposition (PVD), chemical vapor deposition(CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE)and more recently, atomic layer deposition (ALD) among others.Removal/etching is any process that removes material from the wafer.Examples include etch processes (either wet or dry), chemical-mechanicalplanarization (CMP), and the like. Reactive ion etching (RIE), forexample, is a type of dry etching that uses chemically reactive plasmato remove a material, such as a masked pattern of semiconductormaterial, by exposing the material to a bombardment of ions thatdislodge portions of the material from the exposed surface. The plasmais typically generated under low pressure (vacuum) by an electromagneticfield. Semiconductor doping is the modification of electrical propertiesby doping, for example, transistor sources and drains, generally bydiffusion and/or by ion implantation. These doping processes arefollowed by furnace annealing or by rapid thermal annealing (RTA).Annealing serves to activate the implanted dopants. Films of bothconductors (e.g., poly-silicon, aluminum, copper, etc.) and insulators(e.g., various forms of silicon dioxide, silicon nitride, etc.) are usedto connect and isolate transistors and their components. Selectivedoping of various regions of the semiconductor substrate allows theconductivity of the substrate to be changed with the application ofvoltage. By creating structures of these various components, millions oftransistors can be built and wired together to form the complexcircuitry of a modern microelectronic device. Semiconductor lithographyis the formation of three-dimensional relief images or patterns on thesemiconductor substrate for subsequent transfer of the pattern to thesubstrate. In semiconductor lithography, the patterns are formed by alight sensitive polymer called a photo-resist. To build the complexstructures that make up a transistor and the many wires that connect themillions of transistors of a circuit, lithography and etch patterntransfer steps are repeated multiple times. Each pattern being printedon the wafer is aligned to the previously formed patterns and slowly theconductors, insulators and selectively doped regions are built up toform the final device.

The flowchart and block diagrams in the Figures illustrate possibleimplementations of fabrication and/or operation methods according tovarious embodiments of the present invention. Variousfunctions/operations of the method are represented in the flow diagramby blocks. In some alternative implementations, the functions noted inthe blocks can occur out of the order noted in the Figures. For example,two blocks shown in succession can, in fact, be executed substantiallyconcurrently, or the blocks can sometimes be executed in the reverseorder, depending upon the functionality involved.

The descriptions of the various embodiments of the present inventionhave been presented for purposes of illustration, but are not intendedto be exhaustive or limited to the embodiments described. Manymodifications and variations will be apparent to those of ordinary skillin the art without departing from the scope and spirit of the describedembodiments. The terminology used herein was chosen to best explain theprinciples of the embodiments, the practical application or technicalimprovement over technologies found in the marketplace, or to enableothers of ordinary skill in the art to understand the embodimentsdescribed herein.

What is claimed is:
 1. A method of forming a semiconductor device, themethod comprising: forming a fin having a fin bottom region; forming acharged region on a sidewall of the fin bottom region; wherein thecharged region comprises charged particles; wherein the fin bottomregion comprises an undoped semiconductor material; wherein the chargedparticles attract charge carriers in the fin bottom region toward andadjacent to the sidewall of the fin bottom region; and wherein thecharge carriers form a current path through the undoped semiconductormaterial of the fin bottom region.
 2. The method of claim 1, wherein:the charged particles comprise dipoles; the charged region comprises: aninterfacial layer comprising positive charges; and a metal oxide layeradjacent to the interfacial layer, the metal oxide layer comprisingnegative charges; the dipoles comprise the positive charges separatedfrom the negative charges by a predetermined distance; and the chargecarriers comprise electrons.
 3. The method of claim 2, wherein theinterfacial layer comprises a material selected from the groupconsisting of SiO₂ and GeO₂.
 4. The method of claim 2, wherein the metaloxide layer comprises a material selected from the group consisting ofY₂O₃, Lu₂O₃, La₂O₃, and SrO.
 5. The method of claim 1, wherein: thecharged particles comprise dipoles; the charged region comprises: aninterfacial layer comprising positive charges; and a metal oxide layeradjacent the interfacial layer, the metal oxide layer comprisingnegative charges; the dipoles comprise the positive charges separatedfrom the negative charges by a predetermined distance; and the chargecarriers comprise holes.
 6. The method of claim 5, wherein theinterfacial layer comprises a material selected from the groupconsisting of SiO₂ and GeO₂.
 7. The method of claim 5, wherein the metaloxide layer comprises a material selected from the group consisting ofAl₂O₃ and TiO₂.
 8. The method of claim 1, wherein the charged particlesare attracted by a dopant in the charged region.
 9. The method of claim8 further comprising implanting the dopant in the charged region. 10.The method of claim 8 further comprising doping the charged region withthe dopant by annealing the fin bottom region in an ambient comprisingthe dopant.
 11. A method of forming a semiconductor device, the methodcomprising: forming a fin over a substrate; wherein the fin comprises afin bottom region and a fin top region; wherein the fin bottom regioncomprises an undoped semiconductor material; forming a bottom source ordrain (S/D) region in or on the substrate; forming a charged region on asidewall of the fin bottom region, the charged region comprising chargedparticles; forming a bottom spacer over the bottom S/D region andadjacent to the charged region; forming a gate on a sidewall of the fintop region; forming a top spacer on the sidewall of the fin top regionand over the gate; forming a top S/D region on a top surface of the fintop region; wherein the charged particles of the charged region attractcharge carriers in the fin bottom region to the sidewall of the finbottom region; and wherein the charge carriers form a fin bottom regioncurrent path configured to couple current from the bottom S/D regionthrough the undoped semiconductor material of the fin bottom region andinto the fin top region.
 12. The method of claim 11, wherein: thecharged particles comprise dipoles; the charged region comprises: aninterfacial layer comprising positive charges; and a metal oxide layeradjacent to the interfacial layer, the metal oxide layer comprisingnegative charges; and the dipoles comprise the positive chargesseparated from the negative charges by a predetermined distance.
 13. Themethod of claims 12, wherein: the charge carriers comprise electrons;the interfacial layer comprises a material selected from the groupconsisting of SiO₂ and GeO₂; and the metal oxide layer comprises amaterial selected from the group consisting of Y₂O₃, Lu₂O₃, La₂O₃, andSrO.
 14. The method of claim 12, wherein: the charge carriers compriseholes; the interfacial layer comprises a negative charge layer materialselected from the group consisting of SiO₂ and GeO₂; and the metal oxidelayer comprises a material selected from the group consisting of Al₂O₃and TiO₂.
 15. The method of claim 11 further comprising implanting adopant in the charged region, wherein the charged particles areattracted by the dopant in the charged region.
 16. The method of claim11 further comprising doping the charged region with a dopant byannealing the fin bottom region in an ambient comprising the dopant. 17.A semiconductor device comprising: a fin having a fin bottom region; acharged region formed on a sidewall of the fin bottom region; whereinthe charged region comprises charged particles; wherein the fin bottomregion comprises an undoped semiconductor material; wherein the chargedparticles attract charge carriers in the fin bottom region toward andadjacent to the sidewall of the fin bottom region; and wherein thecharge carriers form a current path through the undoped semiconductormaterial of the fin bottom region.
 18. The device of claim 17, wherein:the charged particles comprise dipoles; the charged region comprises: aninterfacial layer comprising positive charges; and a metal oxide layeradjacent to the interfacial layer, the metal oxide layer comprisingnegative charges; the dipoles comprise the positive charges separatedfrom the negative charges by a predetermined distance; the chargecarriers comprise electrons; the interfacial layer comprises a materialselected from the group consisting of SiO₂ and GeO₂; and the metal oxidelayer comprises a material selected from the group consisting of Y₂O₃,Lu₂O₃, La₂O₃, and SrO.
 19. The device of claim 18, wherein: the chargedparticles comprise dipoles; the charged region comprises: an interfaciallayer comprising positive charges; and a metal oxide layer adjacent theinterfacial layer, the metal oxide layer comprising negative charges;the dipoles comprise the positive charges separated from the negativecharges by a predetermined distance; the charge carriers comprise holes;the interfacial layer comprises a material selected from the groupconsisting of SiO₂ and GeO₂; and the metal oxide layer comprises apositive charge layer material selected from the group consisting ofAl₂O₃ and TiO₂.
 20. The device of claim 19, wherein the chargedparticles are attracted by a dopant in the charged region.